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課程名稱 |
交換電路與邏輯設計
SWITCHING CIRCUIT AND LOGIC DESIGN |
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開課學期 |
97-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
盧奕璋 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
04 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四6(13:20~14:10)星期五7,8(14:20~16:20) |
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上課地點 |
電二145電二145 |
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備註 |
本系優先
總人數上限：70人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/971scld_yiclu |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
01 Introduction: Number Systems and Conversion
02 Boolean Algebra
03 Boolean Algebra (continued)
04 Applications of Boolean Algebra: Minterm and Maxterm Expansions
05 Karnaugh Maps
06 Quine-McClusky Method
07 Multi-Level Gate Circuits: NAND and NOR Gates
08 Combinational Circuit Design and Simulation Using Gates
09 Multiplexers, Decoders and PLDs
10 Introduction to Verilog-HDL
11 Latches and Flip-Flops
12 Registers and Counters
13 Analysis of Clocked Sequential Circuits
14 Derivation of State Graphs and Tables
15 Reduction of State Tables: State Assignment
16 Sequential Circuit Design
17 Supplementary materials |
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課程目標 |
Provide students the essential knowledge in logic design. |
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課程要求 |
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預期每週課後學習時數 |
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Office Hours |
另約時間 |
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指定閱讀 |
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參考書目 |
Charles H. Roth, Jr.
Fundamentals of Logic Design, 5e
Thomson, 2004 (required)
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Homework |
17% |
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2. |
Quiz 1 |
4% |
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3. |
Midterm |
35% |
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4. |
Quiz 2 |
7% |
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5. |
Final |
35% |
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6. |
Participation |
2% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/18,9/19 |
Ch 1 Introduction: Number Systems and Conversion; Ch 2 Boolean Algebra
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第2週 |
9/25,9/26 |
Ch 2 Boolean Algebra; Ch 3 Boolean Algebra (cont’d)
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第3週 |
10/02,10/03 |
Ch 4 Application of Boolean Algebra |
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第4週 |
10/09,10/10 |
Ch 5 Karnaugh Maps; 10/10國慶日放假一天
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第5週 |
10/16,10/17 |
10/16 Quiz 1; Ch 5 Karnaugh Maps
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第6週 |
10/23,10/24 |
Ch 7 Multi-Level Gate Circuits: NAND NOR Gates |
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第7週 |
10/30,10/31 |
Ch 8 Combinational Ckt Design (skip 8.1, 8.2) |
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第8週 |
11/06,11/07 |
Ch 9 Multiplexers, Decoders, and Programmable Logic Devices (skip 9.7) |
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第9週 |
11/13,11/14 |
11/13 Review session (TA); 11/14 Midterm
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第10週 |
11/20,11/21 |
Ch 11 Latches and Flip-flops; 11/21 Verilog: Combinational Circuits (TA)
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第11週 |
11/27,11/28 |
Ch 11 Latches and Flip-flops; Ch 12 Registers and Counters
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第12週 |
12/04,12/05 |
Ch 12 Registers and Counters |
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第13週 |
12/11,12/12 |
Ch 13 Analysis of Clock Sequential Ckts |
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第14週 |
12/18,12/19 |
Ch 14 Derivation of State Graphs and Tables
(Skip examples 2 & 3 in Sec. 14.3)
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第15週 |
12/25,12/26 |
12/25 Quiz 2; Ch 15 Reduction of State Tables (15.1 to 15.2)
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第16週 |
1/01,1/02 |
1/1 元旦放假一天; Ch 16 Sequential Ckt Design (16.1 to 16.4)
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第17週 |
1/08,1/09 |
Supplementary materials |
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第18週 |
1/15,1/16 |
1/15 Review session (TA); 1/16 Final exam
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